#ifndef _SDRAM_DDR_DP_DEVICE_IF_H
#define _SDRAM_DDR_DP_DEVICE_IF_H

#include "SDRAM_DDR_define.h"

class SDRAM_DDR_DP_device_if
: public sc_interface
{
public:
	virtual const bool
	SDRAM_refresh(unsigned	port_id,
				  bool		refresh_type) = 0;

	virtual const bool
	SDRAM_row_activate(unsigned		port_id,
					   unsigned		rank_sel,
					   unsigned		bank_sel,
					   SDRAM_addr_t	row_addr) = 0;

	virtual const bool
	SDRAM_read_command(unsigned		port_id,
					   unsigned		rank_sel,
					   unsigned		bank_sel,
					   SDRAM_addr_t	col_addr,
					   bool			auto_precharge) = 0;

	virtual const bool
	SDRAM_write_command(unsigned		port_id,
						unsigned		rank_sel,
						unsigned		bank_sel,
						SDRAM_addr_t	col_addr,
						bool			auto_precharge) = 0;

	virtual const bool
	SDRAM_precharge(unsigned	port_id,
					unsigned	rank_sel,
					unsigned	bank_sel,
					bool		precharge_all) = 0;

	virtual const bool
	SDRAM_DDR_mode_register_set(unsigned		port_id,
								unsigned		EMRS_num,
								unsigned short	EMRS_code) = 0;

	virtual const SDRAM_DDR_data_t
	SDRAM_DDR_read_data(unsigned	port_id,
						unsigned	rank_sel,
						unsigned	bank_sel,
						unsigned	current_burst,
						bool		direct_access) = 0;

	virtual const bool
	SDRAM_DDR_write_data(unsigned			port_id,
						 unsigned			rank_sel,
						 unsigned			bank_sel,
						 unsigned			current_burst,
						 SDRAM_DDR_data_t	data,
						 bool				direct_access) = 0;

	virtual const sc_logic
	SDRAM_DDR_get_DQS(unsigned	port_id,
					  unsigned	rank_sel,
					  unsigned	bank_sel) const = 0;

	virtual const bool
	SDRAM_DDR_set_DQS(unsigned	port_id,
					  unsigned	rank_sel,
					  unsigned	bank_sel,
					  sc_logic	DQS) = 0;
};

#endif